1. Field of the Invention
Generally, the present disclosure relates to the field of integrated circuits, and, more particularly, to integrated circuits wherein semiconductor-on-insulator techniques are employed.
2. Description of the Related Art
Integrated circuits typically include a large number of circuit elements, which include, in particular, field effect transistors. In a field effect transistor, a gate electrode may be separated from a channel region by a gate insulation layer that provides an electrical insulation between the gate electrode and the channel region. Adjacent the channel region, a source region and a drain region are provided.
The channel region, the source region and the drain region are formed in a semiconductor material, wherein the doping of the channel region is different from the doping of the source region and the drain region. Depending on an electric voltage applied to the gate electrode, the field effect transistor may be switched between an on-state and an off-state.
For improving the performance of integrated circuits including field effect transistors, it has been proposed to employ semiconductor-on-insulator technology. In semiconductor-on-insulator technology, the source, channel and drain regions of transistors are formed in a thin layer of a semiconductor material, for example, silicon. The thin layer of semiconductor material is provided above a substrate of a semiconductor material, for example, silicon, and separated from the substrate by an electrically insulating material, for example, silicon dioxide. Compared to integrated circuits wherein field effect transistors are formed on the basis of a bulk semiconductor substrate, semiconductor-on-insulator technology allows reducing parasitic capacitances and leakage currents and a sensitivity of integrated circuits with respect to ionizing radiation.
However, semiconductor-on-insulator technology has some specific issues associated therewith, which include the so-called floating body effect. The body of a semiconductor-on-insulator field effect transistor forms a capacitor with the insulated substrate. On this capacitor, electric charge can accumulate and cause adverse effects, including a dependence of the threshold voltage of the field effect transistor on its previous states and a reduced controllability of the conductance of the channel.
Various approaches have been proposed for improving the performance of semiconductor-on-insulator field effect transistors.
US Patent Publication No. 2011/0291196 discloses a semiconductor device that includes a FinFET or tri-gate transistor on the basis of a semiconductor-on-insulator substrate. The semiconductor device includes a silicon substrate, above which is formed a buried insulating layer, typically in the form of a silicon dioxide material. Furthermore, a plurality of semiconductor fins are provided and represent the “residues” of a silicon layer initially formed on the buried insulating layer. The fins include a source region, a drain region and a channel region. The extension of the channel region along the length direction of the fins is determined by a gate electrode structure including an electrode material, such as polysilicon, and a spacer structure. A gate dielectric material separates the electrode material from the semiconductor material of the channel region at the sidewalls of the fins and, in the case of a tri-gate transistor, on the top surface of the fins. Transistors wherein the channel region is formed in fins may have an improved controllability of the channel.
Furthermore, fully depleted field effect transistors have been proposed. Fully depleted field effect transistors are formed using a semiconductor-on-insulator structure, wherein the semiconductor layer provided on the insulator layer has a smaller thickness than a channel depletion width. Thus, the electric charge and, accordingly, the body potential of the field effect transistor is fixed, which may be helpful for avoiding or at least reducing the floating body effect and for improving channel controllability.
The manufacturing of a fully depleted field effect transistor will be described with reference to FIG. 1. FIG. 1 shows a schematic cross-sectional view of a semiconductor structure 100. The semiconductor structure includes a substrate 101. On the substrate 101, an electrically insulating layer 102 is formed. A semiconductor layer 103 is formed on the electrically insulating layer 102. The substrate 101, the electrically insulating layer 102 and the semiconductor layer 103 provide a semiconductor-on-insulator structure.
A trench isolation 104, which may include a shallow trench isolation structure, separates a portion of the semiconductor layer 103 wherein an active region of a fully depleted field effect transistor 105 is formed from other portions of the semiconductor layer 103 (not shown). On the semiconductor layer 103, a gate structure 106 is provided. The gate structure 106 includes a gate insulation layer 107, which may include a high-k material having a greater dielectric constant than silicon dioxide, and a gate electrode 110 including a metal portion 108 and a polysilicon portion 109. Adjacent the gate electrode 110, a sidewall spacer 112 is provided, which is separated from the gate electrode 110 by a liner layer 111. The field effect transistor 105 further includes a source region 114 and a drain region 116 adjacent the gate structure 106. The source region 114 and the drain region 116 are differently doped than a channel region 115 below the gate electrode 110, and may include source and drain extensions extending below the sidewall spacer 112.
These features may be formed using techniques for providing a semiconductor-on-insulator structure, including oxidation, bonding, cleaving and polishing of semiconductor wafers, and techniques for forming field effect transistors, such as deposition, oxidation, photolithography, etching and ion implantation.
In particular, the formation of the source region 114 and the drain region 116, and the formation of source and drain extensions, may include one or more ion implantation processes, as shown schematically by arrows 113 in FIG. 1.
In an ion implantation process, the semiconductor structure 100 is bombarded with energetic ions of a dopant. The ions are incorporated into the semiconductor material of the semiconductor layer 103 and provide the doping of the source region 114 and the drain region 116. The channel region 115 is protected from the ions by the gate structure 106. While ion implantation processes for forming the source region 114 and the drain region 116 may be performed after the formation of the sidewall spacer 112, ion implantations for forming source and drain extensions may be performed before the formation of the sidewall spacer 112.
However, due to the bombardment of portions of the semiconductor layer 103 with energetic ions in the ion implantation processes, the crystalline structure of the material of the semiconductor layer 103 may be destroyed, so that amorphous material may be obtained in the source region 114 and the drain region 116, and possibly also in the source and drain extensions.
Thus, portions of the semiconductor layer 103 adjacent the gate structure 106 are amorphized. The amorphized material cannot easily be re-healed by means of a thermal annealing process, since, due to the semiconductor-on-insulator structure with the thin semiconductor layer 103 that is employed for forming the fully depleted field effect transistor 105, substantially no crystalline semiconductor material is left below the amorphized material.
The amorphous structure of the source region 114 and the drain region 116 may lead to an increased electrical resistance between the channel region 115 and the source region 114, and between the channel region 115 and the drain region 116. Furthermore, the amorphous structure of the source region 114 and the drain region 116 may lead to an increased contact resistance between the source region 114 and the drain region 116, respectively, and electrical connections thereto, and to an increased leakage current of the field effect transistor 105.
Similar issues as described above in the context of fully depleted field effect transistors may also occur in the formation of semiconductor-on-insulator FinFET or tri-gate transistors.
In view of the situation described above, the present disclosure provides a device and a method wherein some or all of the above-mentioned issues may be overcome or at least reduced.